This invention relates generally to the field of electrical connections for integrated circuits and more particularly relates to the field of land grid array electrical connections.
In the world of integrated circuits, there are a multitude of electrical connections between the integrated circuits and other integrated circuits and eventually to the xe2x80x9coutside world.xe2x80x9d As integrated circuits become more dense, so must the electrical connections. Integrated circuits are mounted on printed circuit boards and printed-wiring technology is the current method to build circuit-boards having embedded circuit traces. These traces are interconnected with vias/microvias which connects one trace on one circuit-board layer to a trace on a different layer. These vias/microvias, however, degrade the continuity of a signal path introducing variations in the electrostatic and electromagnetic qualities of the via transition. Varying and controlling the physics of each connection by controlling the dielectric used, the dielectric thickness, and the area of the signal path can result in a specific, controlled characteristic impedance. Ideally, any portion of any high-density high-speed device should be equally accessed and interconnected with homogenous, impedance-controlled connections to improve signal fidelity with less reflection and reduced electromagnetic interference. Shielding can be added around the outer portions of the wire to shield against electromagnetic field radiation. There are a myriad of options to provide the electrical connections to/from integrated circuits with these considerations incorporated into the design, such as various small outline packages, plastic leaded chip carrier, dual inline packages, pin grid arrays, ball grid arrays, etc.
The next generation of integrated circuits such as system-on-chip and other high-density devices, however, require high density electrical interconnections. Current limitations of printed-wiring boards have trace widths as small as 0.003 inch. While fine, high-density circuit traces increase the density of a interconnect they also increase the inductance, resistance, and current-carrying ability of the interconnect. High-speed, high-density circuit board can be difficult to design when evenly distributed minimum strip-line layers having minimum vias are required. In addition, circuit boards for high-speed, high density having exacting requirements can be expensive to manufacture. Previous packaging options, like pin grid arrays and quad flat packs all left something to be desired in achieving these goals. Even with fine line techniques, larger printed circuit board designs have difficulty reaching the inner portions of high-density devices with homogenous, impedance-controlled connections.
An emerging technology that is becoming increasingly popular is to package the high density, high speed integrated devices without any terminations on the bottom. Such packages are referred to as Land Grid Arrays (LGA). Although not technically accurate, the easiest way to envision an LGA device is to picture a semiconductor with nothing but tiny round gold plated pads on the bottom whereas if the device were a ball grid array, a ball would be soldered to each pad. The biggest reason for terminating a device as an LGA is to achieve higher pin counts (number of outputs) with smaller packages. With new requirements such as high-end printed circuit boards requiring 1000 and more pin counts, even the ball grid array is not an option because the large footprints can not stand the forces on the solder joints that are caused by thermal mismatch, i.e., the materials of the semiconductor device have different coefficients of expansion than those of the target printed circuit board. A xe2x80x9cz-axisxe2x80x9d connection of the LGA can overcome the thermal mismatch problems.
Land grid arrays offer high interconnection density, e.g., at a one millimeter pitch, a 35xc3x9735 grid may contain 1,225 interconnections in a space less than 1.5 square inches and 2,025 interconnections in a 45xc3x9745 grid less than 1.75 square inches. Land grid array modules are easy to manufacture and the cost of module production is must less because terminations such as pins or balls are no longer required. Recall that it is very important to keep the electrical path of each connection as short as possible for low inductance and the LGA achieves this with a distance from the bottom of the device being socketed to the target board of less than two millimeters with some LGA socket designs. Co-planarity problems are reduced in many instances because LGA sockets can be manufactured for spring movement of 0.015xe2x80x3 (0.4 mm) which xe2x80x9ctakes up the slackxe2x80x9d when there is a problem with co-planarity on the bottom of the device. LGAs also have low mating force requirements, in some instances requiring only 20 to 35 grams of force per position to achieve reliable mating. When using land grid arrays, moreover, microprocessors can be easily removed and replaced.
As discussed above almost all LGA interconnections require a LGA connector element where controlled loads are applied to this element using some form of mechanical hardware. Examples of a connector is an interposer or socket component; something that possesses the specific LGA pattern of exposed contacts on top and bottom faces of the connector and mates to corresponding module and board surfaces to be interconnected. To ensure reliable LGA interconnection performance, both contact members in the interposer and mating surfaces of boards and module LGA contact pads must possess a noble surface finish that is both resistant to corrosion and provides low contact resistance within the contact load range necessary for mating of the connector. To provide these attributes on printed circuit boards, LGA contact pads are usually plated with a nickel/gold (Ni/Au) surface finish. In many applications, including some backplane applications, these surfaces must be plated by selective deposition of electrolytic Ni/Au platings as opposed to use of electroless or immersion platings.
Although the use of electrolytic Ni/Au plating provides desirable surface nobility, deposition thickness of the electrolytic platings and particularity the nickel underplating can be quite variable across an LGA site, greater than 0.001xe2x80x3 to 0.002xe2x80x3 on large LGA areas used on some backplanes. The variation of the Ni/Au electrolytic plating thickness typically results from current density variation on specific etched metal surface features of a board; typically higher current densities are more isolated from the bulk of etched surface features. Higher current density causes thicker Ni/Au platings while areas with more surrounding metal surface area have more balanced current density and plate near desired nominal thickness conditions. Indeed, high Ni/Au thickness is observed on exposed outer perimeter row and comer pads of LGA areas on printed circuit boards. Thickness variability observed on multiple LGA printed circuit products is as much as 0.002xe2x80x3, and in severe cases, can exceed 0.004xe2x80x3. This variation ultimately creates significant contact load variation on LGA interposers used to interconnect modules to board surfaces because the pad thickness variation may use up ⅔ of a typical working tolerance of 0.006xe2x80x3. The variable load impedes the ability to design LGA interconnections and loading systems that enable contact formation within a recommended load point range for specific LGA connector technologies to ensure long term contact reliability. Moreover, high points on cards resulting from added plating thickness and plating variability are more sensitive to handling or abrasion damage.
In addition to these issues of contact load variability from inconsistent board plating thickness and sensitivity to plating surface damage are other concerns of potential for degradation of contact surfaces in corrosive environments and sensitivity of board contact surfaces to particulate contamination that can interfere or degrade LGA connector contact function as well.
There is thus a need in the industry to provide a land grid array electrical interconnection that provides more homogeneous and more consistent electrical contacts while protecting the land grid array and the interconnection environment from corrosion resulting from factors such as mechanical friction, unwanted particles, and corrosion.
These objects are thus satisfied by a land grid array on a carrier, the land grid array having a plurality of electrical interconnections having a sash surrounding the perimeter of the land grid array. The height of the sash preferably is the same heights as the electrical interconnections extending above the plane of the carrier. The sash may have a noble or semi-noble surface finish plating; the plating may be a pure metal or an alloy from the group consisting of Ni, Au, or palladium. The sash may be conductive and of the same material as the plurality of electrical interconnections. If the sash is conductive, it may be electrically connected to a logic ground voltage, or another voltage. Indeed, the sash may be manufactured and processed simultaneously with the manufacturing and processing of the electrical interconnections.
The outer perimeter of the conductive sash may be slightly larger than the outer periphery of a frame of an electrical interposer connector to be aligned onto the land grid array. If the array is one for a multichip module, the sash may comprise at least one interior sash surrounding each of a plurality of electrical interconnections specific to one of several individual chip domains residing on the multichip module. The sash may have a plurality of electrical connections connecting it to selected ones of the plurality of electrical interconnections.
The invention may also be considered a land grid array on a carrier, comprising: a plurality of electrical interconnections arranged into an array; an electrically conductive sash surrounding the perimeter of the array, the sash having a width defined by an inner edge closest to the array and an outer edge, the width of the sash larger than a frame having a mating connector to be positioned onto the array, the height of the sash being the same height as the electrical connections; and a plurality of electrical connections between the sash and array at selected electrical connections.
The invention is further considered a carrier with a land grid array for use with a land grid array interposer connector, the land grid array having of multitude of electrical interconnections, comprising: placement means for an interposer to rest upon when placed upon the array; means to provide a more uniform height and surface finish of the electrical interconnections spanning interior regions of the area toward the outer periphery of the array where the interposer is placed upon the placement means; and means to prevent particulate and gaseous contamination of the array of electrical connections when an interposer is placed onto the array. The placement means, the uniform height and surface means, and the prevention means may be an electrically conductive sash of the same material as the electrical connections surrounding the periphery of the array.